A 0.8 V 0.23 nW 1.5 ns full-swing pass-transistor XOR gate in 130 nm CMOS

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dc.citation.volume2013
dc.contributor.authorAhmad N
dc.contributor.authorHasan SMREZAUL
dc.date.available2013-03
dc.date.issued2013-03
dc.description.abstractA power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.
dc.description.confidentialFALSE
dc.format.extent1 - 6 (6)
dc.identifierhttps://www.hindawi.com/
dc.identifierArticle ID 148518
dc.identifier.citationActive and Passive Electronic Components, 2013, 2013 pp. 1 - 6 (6)
dc.identifier.doi10.1155/2013/148518
dc.identifier.elements-id237083
dc.identifier.harvestedMassey_Dark
dc.identifier.issn1563-5031
dc.identifier.urihttps://hdl.handle.net/10179/7467
dc.publisherHindawi Publishing Corporation
dc.publisher.urihttps://www.hindawi.com/
dc.relation.isPartOfActive and Passive Electronic Components
dc.subject.anzsrc0906 Electrical and Electronic Engineering
dc.titleA 0.8 V 0.23 nW 1.5 ns full-swing pass-transistor XOR gate in 130 nm CMOS
dc.typeJournal article
pubs.notesNot known
pubs.organisational-group/Massey University
pubs.organisational-group/Massey University/College of Sciences
pubs.organisational-group/Massey University/College of Sciences/School of Food & Advanced Technology Manawatu
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